1. Field of the Invention
The present invention relates generally to sense amplifiers. More specifically, the present invention relates to a single ended match sense amplifier.
2. Description of the Relevant Art
Sense amplifiers are used in a number of digital circuit applications to enhance the speed of transition time between changes in logic levels on a given address or data line. Often times, this is accomplished by precharging the data or address line to a high voltage representing a logic one just prior to the transmission of a data or address signal. Proper charging of data or address lines requires a certain amount of time because of RC time constants associated with charging the capacitance of the address or data line. To the extent this can be done by a precharge phase between data cycles, time can be saved. A data or address signal may then be introduced on the line, and the voltage value of the line will be selectively changed (or not) in order to represent the state of the data signal.
In one precharging scheme, binary "0" and "1" bits are represented on the data line by 0 volts and some positive voltage, such as 5 volts. If a "0" n bit is transmitted using the data line, the voltage on the data line will be driven down to 0 volts. Otherwise, if a "1" bit is to be transmitted, the line is left at the higher voltage value.
Sense amplifiers are employed in translation lookaside buffers (TLB) to detect or sense a match between an inputted virtual address and the contents of the translation lookaside buffer. TLBs employ match lines which transmit a match signal indicative of a match between an input virtual address and the TLB contents, or a miss signal indicative of a mismatch between the input virtual address and the TLB contents. Prior to transmission of the match or miss signal, the match lines are precharged to a predetermined high voltage, e.g., 5 volts. This predetermined voltage typically represents a match signal for a subsequent translation cycle. The match or miss signal is then introduced on the sense line, and the voltage value of the line will be selectively changed (or not) in order to represent the results of the input address comparison. Sense amplifiers sense the signal on the match lines, and output a corresponding signal in response.
FIG. 1 is a block diagram of the conventional TLB 10 which stores a set of virtual address/physical address translations. TLB 10 includes a content addressable memory (CAM) array 12 of CAM cells for storing virtual addresses, a first random access memory (RAM) array 14 of RAM 1 cells for storing a plurality of special bits used to qualify the virtual to physical address translation, and a second RAM array 16 of RAM2 cells for storing physical addresses corresponding to virtual addresses stored in CAM array 12.
TLB 10 further includes a plurality of CAM write drivers 20, first RAM write drivers 22, and second RAM write drivers 24. Each of the write drivers 20-24 includes a pair of differential inputs, a control input, and a pair of differential outputs.
Each CAM write driver 20 has a pair of differential outputs coupled respectively to a pair of differential bit lines 30 and 32 within CAM array 12. The differential outputs of first RAM write drivers 22 are coupled respectively to differential bit lines 34 and 36 in first RAM array 14. Differential outputs of second RAM write drivers 24 are coupled respectively to differential bit lines 38 and 40 within second RAM array 16.
The control input of each CAM and first RAM write driver, 20 and 22, respectively, is coupled to a CAM/RAM1 write enable signal line 44. Similarly, each control input of second RAM write driver 24 is coupled to RAM2 write enable signal line 46. In general, the write drivers 20-24 write data to their corresponding storage cells in response to receiving a write enable signal. More particularly, CAM write drivers 20 write virtual address signals in the CAM cells via bit lines 30 and 32 when write drivers 20 receive the CAM/RAM1 write enable signal. First RAM write driver 22 write special bit signals to the RAM1 cells via bit lines 34 and 36 when write drivers 22 receive the CAM/RAM1 write enable signal. Second RAM write drivers 24 write physical address signals to RAM2 cells via differential bit lines 38 and 40 when write drivers 24 receive the RAM2 write enable signal.
TLB 10 further includes CAM read sense amplifiers 50, first RAM read sense amplifiers 52, and second RAM read sense amplifiers 54. Each read sense amplifier has a pair of differential inputs, a control signal input, and a pair of differential outputs.
Each pair of differential inputs to CAM read sense amplifier 50 is coupled to a pair of differential bit lines 30 and 32 within CAM array 12. Each pair of differential inputs to first RAM read sense amplifier 52 is coupled to a pair differential bit lines 34 and 36 within first RAM array 14. Each pair of differential inputs of second RAM read sense amplifier 54 is coupled to a pair of differential bit lines 38 and 40 within second RAM array 16.
Each control input of CAM and first RAM read sense amplifiers 50 and 52, respectively, is coupled to a CAM/RAM1 read enable signal line 58. Each control input of second RAM read sense amplifier 54 is coupled to a RAM2 read enable signal line 60.
In general, each read sense amplifier generates a differential output signal as a function of a differential input signal and in response to receiving a read enable signal. Thus, CAM read sense amplifiers 50 output virtual address signals stored in the CAM cells in response to receiving the CAM/RAM1 read enable signal. First RAM read sense amplifiers 52 output special bit signals stored in the RAM1 cells in response to receiving the CAM/RAM1 read enable signal. Second RAM read sense amplifiers 54 outputs physical address signals stored in RAM2 cells in response to receiving the RAM2 read enable signal.
TLB 10 further includes a plurality of CAM/RAM1 word line drivers 64, and a plurality of RAM 2 word line drivers 66. Each CAM/RAM1 word line driver 64 has an output coupled to a row or line of CAM and RAM1 cells within the CAM array 12 and first RAM array 14, respectively, via word line 68. Each RAM2 word line driver 66 is coupled to a row or line of RAM 2 cells in second RAM array 16 via word line 70. Each CAM/RAM1 word line driver 64 generates a word line signal which activates a row of CAM and RAM1 cells. Word line driver 64 generates the word line signal in response to receiving a line address signal from a word line decoder (not shown). Likewise, each RAM2 word line driver 66 generates a word line signal which activates a row of RAM2 cell in response to RAM2 word line driver 66 receiving a line address signal from the word line decoder.
TLB 10 also includes a plurality of match sense amplifiers 74, each of which is coupled to a line of CAM cells within CAM array 12 via a match line 76. In a translation operation, one of the match sense amplifiers 74 sense when a virtual address inputted to CAM array 12 matches a virtual address stored within a line of CAM cells therein. As is to be noted within FIG. 1, each match sense amplifier 74 is coupled to one of the CAM/RAM1 word line drivers 64 and RAM2 word line drivers 66. When match sense amplifier 74 senses a match signal on match line 76 indicating that an input virtual address matches the contents of a row of CAM cells, match sense amplifier 74 outputs a signal to both CAM/RAM1 word line driver 64 and RAM to word line driver 66. Upon receipt of the signal from match sense amplifier 74, CAM/RAM1 word line driver 64 outputs a word line signal to its respective line of CAM and RAM1 cells. Similarly, when match sense amplifier 74 generates its signal, RAM2 word line driver 66 outputs a word line signal to its line of RAM2 cells.
CAM array 12 includes a plurality of CAM cells 80 arranged in x columns and n rows. Each row of CAM cells 80 stores a single x bit virtual address and, as noted above, is coupled to one of the CAM/RAM1 word lines 68. Each column of CAM cells 80 is coupled to a pair of CAM differential bit lines 30, 32, and a pair of CAM differential virtual address lines 82, 84. Each row of CAM cells 80, as noted above, is connected to one of the match lines 76. In an address translation, a virtual address is input to differential CAM virtual address bit lines 82 and 84. Thereafter, internal circuitry within CAM cells 80 compares the input virtual address with the CAM cell contents. If a row of CAM cells 80 stores an address which equates to the input virtual address, a match signal is provided on the corresponding match line 76. If the row of CAM cells 80 does not store the address corresponding to the input virtual address, a miss signal is provided on the corresponding match line 76.
Generally, each match sense amplifier 74 includes precharging circuitry (not shown) which precharges the match lines before an address translation cycle. The precharging circuitry is defined by a transistor coupled between a supply voltage and match line 76. The gate of the transistor is configured to receive a precharge pulse signal. When the transistor is activated by the precharge pulse signal, the transistor conducts current to charge match line 76 to a voltage substaintially equal to the supply voltage. Once precharged, CAM array 12 is provided with an input virtual address. If the virtual address does not equate to the contents of a row of CAM cells, one or more of the CAM cells will operate to discharge the corresponding match line 76 to a voltage substantially equal to ground, thereby providing a missed signal on match line 76. If the row of CAM cells contains an address equal to the input virtual address, none of the CAM cells within the row will discharge match line 76. Thus, match line 76 should keep its precharged voltage, thereby indicating a match signal. Match sense amplifier 74, is timed to generate an output signal indicative of the voltage on match line 76 at a particular instant of time. It is to be noted that within the prior art, each CAM cell 80 in a row is connected to a corresponding match sense amplifier 74 via a single sense line 76.
First RAM array 14 includes a plurality of RAM1 cells 88 arranged in N rows and y columns. Each row of RAM1 cells 88 stores n special bits associated with a virtual address stored in the corresponding line of CAM cells 80. Each row of RAM1 cells 88 is coupled to one of the word lines 68, and thus one of the CAM/RAM1 word line drivers 64. Each column of RAM1 cells 88 is coupled to corresponding pair of differential first RAM bit lines 34 and 36.
Second RAM array 16 comprises a plurality of RAM2 cells 98 arranged in N rows and Z columns. The RAM2 cells 98 are substantially similar to the RAM1 cells 88. Each row of RAM2 cells stores a single z bit physical address. Each row of RAM2 cells 98 is coupled to one of the RAM2 word line drivers 66 via word line 70. Each column of RAM2 cells 98 is coupled to a corresponding pair of differential RAM2 bit lines 38 and 40. When one of the match sense amplifiers 74 detects a match of an input virtual address, the match sense 74 issues a corresponding signal to its associated RAM2 word line driver 66 and CAM/RAM1 word line driver 64, which in turn generates a word line signal to its corresponding rows of RAM2 cells 98 and RAM1 cells 88. In response, the corresponding row of RAM2 cells 98 output their physical address contents to differential bit lines 38 and 40, and the corresponding row of RAM1 cells output their special bits to differential bit lines 34 and 36 . Read sense amplifiers 54 and 52 receive the physical address and special bits at their differential inputs, and acting in response to RAM2 and CAM/RAM2 read enable signals, output the physical address and special bits, which are concatenated and used to access the computer's main memory (not shown).
As noted above, TLB 10 stores the most recently used virtual address/physical address pairs. Often times, TLB 10 must be updated with new virtual address/physical address pairs. TLB 10 is provided with read and write access modes to accomplish content updating. In one write access mode, CAM and first RAM write drivers 20 and 22, respectively, charge differential bit lines 30-36 as a function of data signals received at their inputs, and in response to CAM/RAM write enable signal. Thereafter, one of the CAM/RAM1 word line drivers 64, operating in response to a received line decode signal, generates a word line signal received by a corresponding line of CAM cells 80 and RAM1 cells 88. In response, the line of activated CAM cells 80 and RAM cells 88 store the values on differential lines 30-36. In a read operation, one of the CAM/RAM1 word line drivers 64 again receives a line decode signal and generates a word line signal which activates a row of CAM cells 80 and RAM1 cells 88. In response, the activated CAM cells 80 and RAM1 cells 88 output their stored contents onto differential bit lines 30-36. CAM read sense amplifiers 50 and first RAM read sense amplifiers 52 detect the voltage values at their inputs, and in response to a CAM/RAM1 read enable signal on line 58, generate corresponding values at their outputs. Second RAM array 16 is accessed in a similar fashion. It is to be noted that CAM array 12 and first RAM array 14 are accessed concurrently, while second RAM array 16 can be accessed independently of CAM array 12 and first RAM array 14 access.
Several problems exist with prior art match sense amplifiers 74. In particular, the proper sensing of a match or missed signal on match line 76 is difficult since match line 76 is substantially long and thus loaded with large capacitance. The large capacitance adds a significant time delay in sensing a match or missed signal on sense line 76 by match sense amplifier 74. One prior art solution to the increased time delay is to employ a differential match sense amplifier. Unfortunately, differential match sense amplifiers are significantly more complicated and occupy significant area on the integrated circuit. Differential sense amplifiers are more sensitive to process variations, and thus, less reliable than their single ended counterparts. Thus, single ended match sense amplifiers, as shown in FIG. 1, are advantageous, except for the speed limitations imposed by the large RC time constant of sense line 76.
Another problem associated with the prior art sense amplifier 74 shown in FIG. 1 relates to charge leakage from sense line 76 during a data or address translation compare cycle. FIG. 2 is a timing diagram illustrating the problems associated with charge leakage from sense line 76. At time t.sub.0, a precharge control signal is provided to a precharge device (not shown) coupled between a supply voltage and sense line 76. The precharge device operates to conduct the current for precharging line 76 to a voltage substantially equal to the supply voltage. At time t.sub.2, the precharge signal is deasserted to a logic high, thereby decoupling the precharge device from sense line 76. Oftentimes, the precharge voltage on sense line 76 begins to degrade due to charge leakage through any one of a number of devices coupled to sense line 76. At time t.sub.3 a virtual address is provided to CAM array 12. If the virtual address matches the contents of the CAM cells coupled to the match line represented in FIG. 2, the voltage on sense line 76 theoretically should remain high, thus indicating a match signal condition. However, charge leakage from sense line 76 may cause the voltage thereon to further decline possibly to a voltage level below the sensing level of match sense amplifier 74. This could cause match sense amplifier 74 to sense a missed condition when, in fact, a match condition should exist.
If the virtual address provided to CAM array 12 does not match the contents within the line of CAM cells, the voltage on sense line 76 will discharge to ground through one or more of the CAM cells, thus indicating a missed condition. At time t.sub.3, when the input virtual address is removed, the voltage on sense line 76 experiences a instantaneous drop. The drop may be on the order of 450 millivolts and may cause the sense line voltage to a valua below low ground. This presents adverse affects to the operation of the sense line amplifier 74. Namely, when the voltage on the sense line is pulled down to a level below ground (VSS) the drains of transistors within compare circuitry of the CAM cells are at a potential less than that of the substrate. As a result, the diode made up by the substrate and the drain may be forward biased causing charge injection from the substrate. This is undesirable and in an extreme case could cause latch up which may adversely affect future operation of the CAM cell.
At time t.sub.5, the precharge signal once again is asserted thereby charging sense line 76 to its precharge level. Clearly, during each sense period between t.sub.2 and t.sub.5, the sense amplifier may detect a false miss due to charge leaking from sense line 76. Moreover, the negative voltage spike on the sense line may cause further adverse effects.